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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.5k 640

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.6k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.7k 263

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.2k 364

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 912 233

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 748 178

Repositories

Showing 10 of 112 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 21 Apache-2.0 30 82 (2 issues need help) 11 Updated Dec 8, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 129 Apache-2.0 75 200 75 Updated Dec 8, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 34 Apache-2.0 31 68 8 Updated Dec 8, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 350 ISC 83 46 (4 issues need help) 29 Updated Dec 8, 2025
  • chipsalliance/chips-alliance-website’s past year of commit activity
    SCSS 4 MIT 7 8 8 Updated Dec 8, 2025
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 306 Apache-2.0 90 27 5 Updated Dec 8, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 303 Apache-2.0 41 18 29 Updated Dec 8, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 120 Apache-2.0 70 88 19 Updated Dec 8, 2025
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 37 Apache-2.0 14 14 4 Updated Dec 8, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 7 5 0 0 Updated Dec 8, 2025